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    Lexers for hardware descriptor languages.

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    :license: BSD, see LICENSE for details.
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    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    ÚverilogÚvz*.vztext/x-verilogú(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`defineÚmacroú\s+ú(\\)(\n)ú/(\\\n)?/(\n|(.|\n)*?[^\\]\n)ú/(\\\n)?[*](.|\n)*?[*](\\\n)?/ú[{}#@]úL?"Ústringú4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'ú%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?ú(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?ú[~!%^&*+=|?:<>/-]ú[()\[\],.;\']ú`[a-zA-Z_]\w*ú^(\s*)(package)(\s+)ú^(\s*)(import)(\s+)Úimport)qÚalwaysÚalways_combÚ	always_ffÚalways_latchÚandÚassignÚ	automaticÚbeginÚbreakÚbufÚbufif0Úbufif1ÚcaseÚcasexÚcasezÚcmosÚconstÚcontinueÚdeassignÚdefaultÚdefparamÚdisableÚdoÚedgeÚelseÚendÚendcaseÚendfunctionÚendgenerateÚ	endmoduleÚ
endpackageÚendprimitiveÚ
endspecifyÚendtableÚendtaskÚenumÚeventÚfinalÚforÚforceÚforeverÚforkÚfunctionÚgenerateÚgenvarÚhighz0Úhighz1ÚifÚinitialÚinoutÚinputÚintegerÚjoinÚlargeÚ
localparamÚmacromoduleÚmediumÚmoduleÚnandÚnegedgeÚnmosÚnorÚnotÚnotif0Únotif1ÚorÚoutputÚpackedÚ	parameterÚpmosÚposedgeÚ	primitiveÚpull0Úpull1ÚpulldownÚpullupÚrcmosÚrefÚreleaseÚrepeatÚreturnÚrnmosÚrpmosÚrtranÚrtranif0Úrtranif1ÚscalaredÚsignedÚsmallÚspecifyÚ	specparamÚstrengthr   Ústrong0Ústrong1ÚstructÚtableÚtaskÚtranÚtranif0Útranif1ÚtypeÚtypedefÚunsignedÚvarÚvectoredÚvoidÚwaitÚweak0Úweak1ÚwhileÚxnorÚxorú\b©Úsuffix)Ú
accelerateÚautoexpand_vectornetsÚ
celldefineÚdefault_nettyper@   ÚelsifÚendcelldefineÚendifÚ
endprotectÚendprotectedÚexpand_vectornetsÚifdefÚifndefr   ÚnoaccelerateÚnoexpand_vectornetsÚnoremove_gatenamesÚnoremove_netnamesÚnounconnected_driveÚprotectÚ	protectedÚremove_gatenamesÚremove_netnamesÚresetallÚ	timescaleÚunconnected_driveÚundefú`)Úprefixrš   )4ÚbitsÚ
bitstorealÚbitstoshortrealÚcountdriversÚdisplayÚfcloseÚfdisplayÚfinishÚfloorÚfmonitorÚfopenÚfstrobeÚfwriteÚ
getpatternÚhistoryÚincsaverZ   ÚitorÚkeyÚlistÚlogÚmonitorÚ
monitoroffÚ	monitoronÚnokeyÚnologÚprinttimescaleÚrandomÚreadmembÚreadmemhÚrealtimeÚ
realtobitsÚresetÚreset_countÚreset_valueÚrestartÚrtoiÚsaveÚscaleÚscopeÚshortrealtobitsÚ
showscopesÚshowvariablesÚshowvarsÚ	sreadmembÚ	sreadmemhÚstimeÚstopÚstrobeÚtimeÚ
timeformatÚwritez\$)ÚbyteÚshortintÚintÚlongintr[   ræ   ÚbitÚlogicÚregÚsupply0Úsupply1ÚtriÚtriandÚtriorÚtri0Útri1ÚtriregÚuwireÚwireÚwandÚworshortrealÚrealrÓ   ú[a-zA-Z_]\w*:(?!:)ú\$?[a-zA-Z_]\w*ú\\(\S+)ú"ú#popú/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})ú	[^\\"\n]+ú\\ú[^/\n]+ú/[*](.|\n)*?[*]/z//.*?\nú/ú	(?<=\\)\nú\nú	[\w:]+\*?©Úrootr   r   r'   c                 C   s8   d}d| v r
|d7 }d| v r|d7 }d| v r|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   rï   gš™™™™™¹?rù   r-   © )ÚtextÚresultr  r  ú5/usr/lib/python3/dist-packages/pygments/lexers/hdl.pyÚanalyse_text„   s   zVerilogLexer.analyse_textN)%Ú__name__Ú
__module__Ú__qualname__Ú__doc__ÚnameÚaliasesÚ	filenamesÚ	mimetypesÚ_wsr	   ÚPreprocr   r   r   ÚEscapeÚSingleÚ	Multiliner   ÚCharr   ÚFloatÚHexÚBinÚIntegerÚOctr
   r   ÚConstantr   Ú	Namespacer   r   ÚBuiltinÚTypeÚLabelÚtokensr  r  r  r  r  r      sŽ    
ÿïîùø
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öüûµNû
ú
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   @   s<  e Zd ZdZdZddgZddgZdgZdZg de	e
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ƒf‘dejf‘dejf‘def‘dedf‘dejf‘dejf‘dejf‘dejf‘dejf‘dejf‘dejf‘def‘dejf‘def‘eddd �ejf‘d!ef‘d"ejf‘ed#dd �ef‘d$e	ej e
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ej!ƒf‘ed'dd �ej"f‘ed(dd �ejf‘ed)dd �ej#f‘d*ej$f‘d+ef‘d,ef‘d-ed.fd/ejfd0efde	eje
ƒfd1efgd2ejfd3ejfd4ejd.fd5ejfd6ejfd7e
d.fgd8ejd.fgd9œZ%d:S );r   z„
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    ÚsystemverilogÚsvz*.svz*.svhztext/x-systemverilogr   z^(\s*)(`define)r   r%   r&   r'   r   r   r   r   r   r   r   r   r    r!   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r"   )ÚinsideÚdistr˜   r™   z[()\[\],.;\'$]r$   )ÒÚ	accept_onÚaliasr(   r)   r*   r+   r,   Úassertr-   Úassumer.   Úbeforer/   ÚbindÚbinsÚbinsofr0   r1   r2   r3   r4   r5   r6   ÚcellÚcheckerÚclockingr7   ÚconfigÚ
constraintÚcontextr9   ÚcoverÚ
covergroupÚ
coverpointÚcrossr:   r;   r<   Údesignr=   r>   r?   r@   rA   rB   Ú
endcheckerÚendclockingÚ	endconfigrC   rD   ÚendgroupÚendinterfacerE   rF   rG   Ú
endprogramÚendpropertyÚendsequencerH   rI   rJ   rK   Ú
eventuallyÚexpectÚexportÚexternrM   Úfirst_matchrN   rO   ÚforeachrP   rQ   ÚforkjoinrR   rS   rT   ÚglobalrU   rV   rW   ÚiffÚifnoneÚignore_binsÚillegal_binsÚimpliesÚ
implementsr'   Úincdirr   rX   rY   rZ   ÚinstanceÚinterconnectÚ	interfaceÚ	intersectr\   Újoin_anyÚ	join_noner]   ÚletÚliblistÚlibraryÚlocalr^   r_   Úmatchesr`   Úmodportra   rb   rc   ÚnettypeÚnewÚnexttimerd   re   Únoshowcancelledrf   rg   rh   Únullri   rj   Úpackagerk   rl   rm   rn   ro   ÚpriorityÚprogramÚpropertyr­   rp   rq   rr   rs   Úpulsestyle_ondetectÚpulsestyle_oneventÚpureÚrandÚrandcÚrandcaseÚrandsequencert   ru   Ú	reject_onrv   rw   Úrestrictrx   ry   rz   r{   r|   r}   Ús_alwaysÚs_eventuallyÚ
s_nexttimeÚs_untilÚs_until_withr~   ÚsequenceÚshowcancelledr€   ÚsoftÚsolver�   r‚   ÚstaticÚstrongr„   r…   r†   ÚsuperÚsync_accept_onÚsync_reject_onr‡   Útaggedrˆ   r   Ú
throughoutÚtimeprecisionÚtimeunitr‰   rŠ   r‹   r�   ÚunionÚuniqueÚunique0ÚuntilÚ
until_withÚuntypedÚuser�   Úvirtualr’   Ú
wait_orderÚweakr“   r”   r•   ÚwildcardÚwithÚwithinr–   r—   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!rí   ré   Úchandler8   rL   rë   r[   rî   rì   rü   rÓ   rï   rê   Ú	shortrealr   r   ræ   rŒ   rŽ   r�   r‘   rð   rñ   rò   ró   rô   r÷   rõ   rö   rø   rú   rù   Úwor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
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$countbitsz
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    For VHDL source code.

    .. versionadded:: 1.5
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(end)(\s+)ÚendblockÚtypesÚkeywordsÚnumbersz	[a-z_]\w*ú;r  )Úbooleanrí   Ú	characterÚseverity_levelr[   ræ   Údelay_lengthÚnaturalÚpositiver   Ú
bit_vectorÚfile_open_kindÚfile_open_statusÚ
std_ulogicÚstd_ulogic_vectorÚ	std_logicÚstd_logic_vectorr   rŽ   )_ÚabsÚaccessÚafterr0  Úallr,   ÚarchitectureÚarrayr1  Ú	attributer/   ÚblockÚbodyÚbufferÚbusr4   Ú	componentÚconfigurationÚconstantÚ
disconnectÚdowntor@   rŸ   rA   ÚentityÚexitÚfilerN   rR   rS   ÚgenericÚgroupÚguardedrW   ÚimpureÚinÚinertialrY   ÚisÚlabelra  ÚlinkageÚliteralÚloopÚmapÚmodrb   rf  Únextre   rf   ri  ÚofÚonÚopenri   ÚothersÚoutrj  ÚportÚ	postponedÚ	procedureÚprocessrp  ÚrangeÚrecordÚregisterÚrejectÚremrx   ÚrolÚrorÚselectÚseverityÚsignalÚsharedÚslaÚsllÚsraÚsrlÚsubtypeÚthenÚtoÚ	transportrŒ   ÚunitsrŒ  r�  Úvariabler’   Úwhenr•   r”  r–   r—   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r  r   r¡  r¢  r£  N)&r  r  r  r  r  r  r  r  ÚreÚ	MULTILINEÚ
IGNORECASEÚflagsr   r   r   r  r	   r  r  r
   r   Ú	Attributer   r   r&  r   r›  r   r   r   r(  r   r#  r   r!  r$  r"  r*  r  r  r  r  r   u  s’    ÿÿÿÿ
ÿÿÿþÿÝ&üüûÿ	ðïÿú
¸r   )r  rò  Úpygments.lexerr   r   r   r   r   r   Úpygments.tokenr   r	   r
   r   r   r   r   r   r   Ú__all__r   r   r   r  r  r  r  Ú<module>   s    
 ,~ d